1. Field of the Invention
This invention pertains generally to integrated circuit fabrication, and more particularly to power minimization including power minimization within Dual-Vdd buffer circuitry.
2. Description of Related Art
As VLSI circuits are aggressively scaled down, the interconnections have become performance bottlenecks. Buffer insertion is extensively relied-upon to reduce interconnect delay at the expense of increased power dissipation. In order to address this problem, one researcher presented a dynamic programming based algorithm for delay-optimal buffer insertion. (Refer to article from L. P. P. P. van Ginneken, “Buffer Placement In Distributed RC-Tree Networks For Minimal Elmore Delay”, printed in proceedings of IEEE Int. Symp. on Circuits and Systems, pp. 865.868, 1990.) Given a routing tree, partial solutions in each tree node are constructed and propagated in a bottom-up fashion. When the optimal solution is identified in the root node, a top-down back-trace is performed to get the optimal buffer assignment. Following this dynamic programming framework, various delay optimization buffer insertion algorithms have been developed in the existing literature, such as a proposal for wire segmenting with buffer insertion; for handling multi-source nets repeater insertion; considering noise and delay optimization simultaneously in buffer insertion; presenting an efficient algorithm for delay-optimal buffer insertion with O(n log n) time complexity by employing a sophisticated data structure. Buffer insertion with variations on wire length and fabrication were considered by other researchers. Power dissipation, however, was not considered in this research.
Buffer insertion can readily increase power dissipation if an excessive number of buffers are included. To leverage power efficiency and circuit performance, the team of J. Lillis, C. Cheng, and T. Lin, proposed a power-optimal buffer insertion algorithm toward achieving low power buffer insertion to given routed tree topologies based on utilizing timing slacks of tree branches. (Refer to article by J. Lillis, C. Cheng, and T. Lin, entitled: “Optimal Wire Sizing And Buffer Insertion For Low Power And A Generalized Delay Model”, in ICCAD, November 1995.) The dynamic programming framework was adopted in this algorithm, wherein the number of options at each node grows in a pseudo-polynomial manner, as computation progresses from sinks to source. The runtime for large nets is unacceptably high due to the uncontrolled option increase. Another researcher assumed a large buffer library with near continuous buffer sizes toward solving the power-optimal buffer insertion problem with 5× speedup and negligible loss of delay and power optimality. However, single-Vdd is assumed in all existing work for power optimal buffer insertion.
Recently, Vdd-programmable buffers have been used to reduce FPGA interconnect power. As buffers are pre-placed, and the dual-Vdd buffer routing is simplified to dual-Vdd assignment. However, the power optimal dual-Vdd buffer insertion problem in ASIC designs is more complicated because the flexible buffer locations in interconnects introduce more design freedom, which increase the solution space substantially. This problem has not been addressed by the existing bodies of work.
Accordingly, a need exists for power saving VLSI circuit design and methods of dual-Vdd buffer insertion which provide power savings with low overhead. The buffer insertion and tree construction techniques described herein fulfill these needs and others while overcoming drawbacks with existing techniques.